Mikko Kotila

Topics: Computing

Computing

Event Latency Scaled --- --- --- 1 CPU cycle 0.3 ns 1 s Level 1 cache access 0.9 ns 3 s…

EventLatencyScaled
1 CPU cycle0.3 ns1 s
Level 1 cache access0.9 ns3 s
Level 2 cache access2.8 ns9 s
Level 3 cache access12.9 ns43 s
Main memory access (DRAM, from CPU)120 ns6 min
Solid-state disk I/O (flash memory)50–150 µs2–6 days
Rotational disk I/O1–10 ms1–12 months
Internet: San Francisco to New York40 ms4 years
Internet: San Francisco to United Kingdom81 ms8 years
Internet: San Francisco to Australia183 ms19 years
TCP packet retransmit1–3 s105–317 years
OS virtualization system reboot4 s423 years
SCSI command time-out30 s3 millennia
Hardware (HW) virtualization system reboot40 s4 millennia
Physical system reboot5 m32 millennia

Table 2.2, Example Time Scale of System Latencies, from Brendan Gregg’s Systems Performance.

Time Scale of System Latencies